Introduction to SDR: Part2

Changing Radio Configuration parameters

We can change and apply radio hardware parameters and tune radio properties before transmitting or receiving signals.Following properties can be changed:

• Baseband Sampling Rate and Filter Chains
• DC Blocking
• Intermediate Frequency Tuning

Now let us discuss all of them in more detail.

1. Baseband Sampling Rate and Filter Chains: 

          To set up the baseband sampling rate and filter chains for radio hardware, use a combination of            two parameters or properties.

• For a receiver System object™ or block, set both the ADC rate and decimation factor.
• For a transmitter System object or block, set both the DAC rate and interpolation factor.

Decimation Factors: 

The FPGA image includes a decimation filter chain, which is controlled by the Decimation Factor parameter or property on the transmitter block or System object. 

The filter chain consists of a CIC filter followed by two halfband filters.

The first halfband filter has a wider transition band and fewer filter weights than the second one.
For this reason, the first halfband is called halfband lightweight (HBL) and the second is called halfband heavyweight (HBH).

The filter chain supports decimation factors from this set of values:

[1:128,130:2:256,260:4:512]

that is,

Any integer from 1 to 128

A multiple of 2 from 130 to 256

A multiple of 4 from 260 to 512

The CIC filter has a variable decimation factor (CIC rate) from 2 through 128, which you can bypass.

Each halfband filter decimates by a factor of 2. You can bypass these filters too. The filters are enabled or bypassed according to these rules:

• If the decimation factor is divisible by 4, then both HBL and HBH are enabled.
• If the decimation factor is divisible by 2 and not by 4, then HBL is bypassed and HBH is enabled.
• If the decimation factor is not divisible by 2, then HBL and HBH are both bypassed.
• The remaining decimation factor is made up by the CIC filter. If the remaining factor is 1, then the CIC is bypassed.

NOTE: The receiver block or System object incorporates the logic to determine these settings automatically from the specified Decimation factor parameter or property.

Interpolation Factors

The FPGA image includes an interpolating filter chain, which is controlled by the Interpolation Factor parameter or property on the transmitter block or System object.
The filter chain consists of two halfband filters followed by one CIC filter.

The first halfband filter has a sharper transition band and more filter weights than the second one. For this reason, the first halfband is called halfband heavyweight (HBH) and the second is called halfband lightweight (HBL).

The filter chain supports interpolation factors from this set of values:

[1:128, 130:2:256, 260:4:512]

that is,

• Any integer from 1 to 128
• A multiple of 2 from 130 to 256
• A multiple of 4 from 260 to 512

Each halfband filter interpolates by a factor of 2, which you can bypass. The CIC filter has a variable interpolation factor (CIC rate) of from 2 through 128. This filter can also be bypassed. The filters are enabled or bypassed according to these rules:

• If the interpolation factor is divisible by 4, then both HBH and HBL are enabled.
• If the interpolation factor is divisible by 2 and not by 4, then HBH is enabled and HBL is bypassed.
• If the interpolation factor is not divisible by 2, then HBH and HBL are both bypassed.
• The remaining interpolation factor is made up by the CIC filter. If the remaining factor is 1, then the CIC is bypassed.

Note: The receiver block or System object incorporates the logic to determine these settings automatically from the interpolation factor parameter or property you specify.

2. DC Blocking

Direct conversion receivers often impose a DC bias on the in-phase and quadrature components of the signal. DC bias, if not dealt with, leads to degraded BER performance for QAM systems, and to a lesser extent, PSK systems.

With DC blocking enabled, DC bias is reduced in the I/Q channels of a received complex signal.

The reduced DC bias better enables robust receiver processing

3. Intermediate Frequency Tuning

• Intermediate frequency (IF) tuning supports second-stage tuning for the transmit and receive data paths. 

• The tuner is configurable at run time (tunable) and provides finer resolution when compared to the primary tuner on an RF card. 

• The tuner also enables you to remove unwanted interference from the passband of interest.

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ZedBoard and FMCOMMS1 RevB/C Transmitter

The ZedBoard and FMCOMMS1 RevB/C Transmitter block is a signal source that sends data to a Xilinx® ZedBoard™ with Analog Devices™ FMCOMMS1 RevB/C RF card on the same Ethernet subnetwork.

DATA FLOW FROM MATLAB TO HARDWARE 

Input to Transmitter Block

The input port supports the following complex and real data types:

• Double-precision floating point
• Single-precision floating point
• 16-bit signed integers

NOTE: All input must be framed based.

Output of Transmitter Block

When you select a double or single data type, the complex values are in the range of [-1,1] and converted to int16.
When you select int16, the complex values are 16-bit I and Q samples that are then sent to the radio hardware.

Following are the parameters that need to be set for the transmitter block.

Center frequency (Hz)

The value can be chosen using a Dialog, and specify the center frequency as a double-precision, nonnegative, finite scalar.
The default is 2.4 GHz.
The valid range of values for this parameter is 400MHz–4GHz.

Intermediate frequency (Hz)

The intermediate frequency (IF) tuner allows you to account for the error in tuning between target center frequency and actual center frequency and avoid unwanted interference by shifting the error out of the passband of interest.
The default value is 0 Hz. The valid range of values for this parameter is  to , where  is the digital-analog converter (DAC) rate.

DAC sampling rate (Hz)

Specify the sampling rate as a double precision, nonnegative scalar. The default value is 98 MHz. The valid range of this parameter is 25–125 MHz.

Interpolation factor


Specify the interpolation factor as a double precision, nonnegative scalar. The default is 512.

IMP- The baseband rate is DAC sampling rate divided by the Interpolation factor.


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ZedBoard and FMCOMMS1 RevB/C Receiver

The ZedBoard and FMCOMMS1 RevB/C Receiver block is a signal source that receives data from a Xilinx® ZedBoard™ with Analog Devices™ FMCOMMS1 RevB/C RF card on the same Ethernet subnetwork.

The ZedBoard and FMCOMMS1 RevB/C Receiver block outputs a matrix signal where each column is a channel of data of fixed length. 

The data length port, DataLength, indicates when valid data is present. When the data length port contains a zero value, there is no data. 

You can use the data length with an enabled subsystem to qualify the execution of part of the model.

Output Data:

The output port supports the following complex data types only:

• Double-precision floating point
• Single-precision floating point
• 16-bit signed integers

NOTE:  When you select a double or single data type, the complex values are scaled to the range of [-1,1]. When you select int16, the complex values are the raw 16-bit I and Q samples from the board.

Following are the parameters that need to be set for the receiver block.

Intermediate frequency (Hz)

The intermediate frequency (IF) tuner allows you to account for the error in tuning between target center frequency and actual center frequency and avoid unwanted interference by shifting the error out of the passband of interest. If you choose Dialog, specify the center frequency as a double-precision, finite scalar. The default value is 0 Hz. The valid range of values for this parameter is  to , where  is the analog-digital converter (ADC) rate.

Gain (dB)

Sets gain on the RF card.

Choose either Dialog or Input port as the source of the overall gain value. If you choose Dialog, specify the gain as a double precision, nonnegative scalar. The default value and the valid range of this parameter depend on the RF card. This parameter is tunable.

ADC sampling rate (Hz)

Specify the sampling rate as a double precision, nonnegative scalar. The default value is 98 MHz. The valid range of this parameter is 20–105 MHz.

Decimation factor

Specify the decimation factor as a double precision, nonnegative scalar. 

The default is 512. 

The baseband rate is the ADC sampling rate divided by the Decimation factor. 

Important - Sample time

Specify the sample time for a single radio sample. For the Simulink sample time to correspond to real time, use the following formula: Sample time = 1/(ADC sampling rate/Decimation factor). The default setting for this parameter is 1.

Frame length

Specify a positive scalar integer for the frame length of the output signal. Values less than 366 can yield poor performance. The default value is 3660.

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Sampling Rates

Sample Time in FMCOMMS1 RevB/C Receiver Block.